1. Field of the Invention
The present invention relates to a method for producing a semiconductor device using a crystalline thin film semiconductor.
2. Description of the Related Art
Recently, much attention is paid on a transistor constructed of a thin film semiconductor formed on a glass or quartz substrate. Such a thin film transistor (TFT) is constructed of a thin film semiconductor having a thickness of several hundreds to several thousands of angstroms (Å) formed on the surface of a glass substrate or a quartz substrate (insulated gate field effect transistor).
TFTs are used in an application field such as the field of an active matrix type liquid crystal display device. An active matrix type liquid crystal display device has several hundred thousands of pixels arranged in a matrix, and TFTs are provided to each of the pixels as switching elements to realize a high quality image display. Practically available TFTs designed for active matrix type liquid crystal display devices utilize thin films of amorphous silicon.
However, TFTs based on thin films of amorphous silicon are still inferior in performance. If a higher display function is required as a liquid crystal display of an active matrix type, the characteristics of TFTs utilizing an amorphous silicon film are too low to satisfy the required level.
Further, it is proposed to fabricate an integrated liquid crystal display system on a single substrate by using TFTs to realize not only the pixel switching, but also the peripheral driver circuit. However, a TFT using an amorphous silicon thin film cannot constitute a peripheral driver circuit because of its low operation speed. In particular, a basic problem is that a CMOS circuit is unavailable from a amorphous silicon thin film. This is due to the difficulty in implementing a practical P-channel type TFT by using amorphous silicon thin film (i.e., the TFT using an amorphous silicon thin film is practically unfeasible due to its too low performance).
Another technology is proposed to integrate other integrated circuits and the like for processing or recording image data, etc., on a single substrate together with the pixel regions and the peripheral driver circuits. However, a TFT using a thin film of amorphous silicon is too inferior in characteristics to constitute an integrated circuit capable of processing image data.
On the other hand, there is a method for manufacturing a TFT using a crystalline silicon film which is far superior in characteristics as compared with the one using a thin film of amorphous silicon. The method for manufacturing TFT comprises the steps of: forming an amorphous silicon film; and modifying the resulting amorphous silicon film into a crystalline silicon film by subjecting the amorphous silicon film to heat treatment or to laser irradiation. The crystalline silicon film obtained by crystallizing an amorphous silicon film generally yields a polycrystalline structure or a microcrystalline structure.
As compared with a TFT using an amorphous silicon film, a TFT having far superior characteristics can be obtained by using a crystalline silicon film. In mobility which is one of the indices for evaluating a TFT, a TFT using amorphous silicon film yields 0.5 to 1 cm2/Vs or lower (in an N-channel TFT), but a TFT using a crystalline silicon film has a mobility of about 100 cm2/Vs or higher in an N-channel TFT, or about 50 cm2/Vs or higher for a P-channel TFT.
The crystalline silicon film obtained by crystallizing an amorphous silicon film has a polycrystalline structure. Hence, various problems arise due to the presence of grain boundaries. For example, carriers which move through the grain boundaries greatly limit the withstand voltage of the TFT. The change or degradation in characteristics which occurs in high speed operation is another problem. Further, the carriers which move through the grain boundaries increase the OFF current (leak current) when the TFT is turned off.
In manufacturing a liquid crystal display device of an active matrix type in a higher integrated constitution, it is desired to form not only the pixel region but also the peripheral circuits on a single glass substrate. In such a case, it is required that the TFTs provided in the peripheral circuit operate a large current to drive several hundred thousands of pixel transistors arranged in the matrix.
A TFT having a wide channel width must be employed to operate a large current. However, even if the channel width should be extended, a TFT using a crystalline silicon film cannot be put into practice because of the problems of withstand voltage. The large fluctuation in threshold voltage is another hindrance in making the TFT practically feasible.
A TFT using a crystalline silicon film cannot be applied to an integrated circuit for processing image data because of problems concerning the fluctuation in threshold voltage and the change in characteristics with passage of time. Accordingly, a practically feasible integrated circuit based on the TFTs which can be used in place of conventional ICs cannot be realized.
To overcome the problems concerning TFTs using a thin film of amorphous silicon or TFTs using a thin film of polycrystalline or microcrystalline silicon, a method for manufacturing a TFT using a particular region is known in the art. The method for manufacturing a TFT comprises steps of forming a region which can be regarded as a single crystal in a particular region of an amorphous silicon thin film, and then forming a TFT utilizing this particular region. By employing the method, a TFT which exhibits characteristics well comparable to those of a transistor formed on a single crystal silicon wafer (i.e., a MOS type transistor) can be obtained.
The above technology is disclosed in JP-A-Hei-2-140915 (the term “JP-A-” signifies “Unexamined Published Japanese Patent Application”). In FIG. 2A, the method comprises the steps of forming a region 201 provided as a seed crystal, and then applying heat treatment to perform crystal growth from the region 201 as the seed crystal in a direction of an arrow 203 to finally crystallize a region of amorphous silicon patterned into a shape 202.
However, in FIG. 2A according to a conventional method, crystal growth occurs from a region 204 simultaneously with the crystal growth that is initiated from the region 201 in which the amorphous silicon patterned into the shape 202 is used as the seed crystal. That is, when the method of FIGS. 2A and 2B is employed, unwanted seeds of crystal growth is formed additionally in the region 204 to allow crystal growth to occur in plural modes. Thus, a polycrystalline state comprising internal crystal grain boundaries is obtained. In heat treatment, crystal growth cannot be performed within a desired area.